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T-Comm_Article 1_3_2020

FPGA LDPC DECODER IMPLEMENTATION AND OPTIMIZATION ITS POWER CONSUMPTION

Maksim Y. Zinchenko, National Research University “MPEI” Moscow, Russia, ZinchenkoMY@gmail.com
Alexey M. Levadniy, National Research University “MPEI” Moscow, Russia, LevadniyAM@gmail.com
Yuri A. Grebenko, National Research University “MPEI” Moscow, Russia, GrebenkoYA@mpei.ru

Abstract
Modern radio communication systems claim highly reliable data transmission over noisy channels. In this connection, noiseless coding has become an essential step in the digital processing of information data. To date, there are a large number of error-correcting codes, one of the most popular are low-density parity check codes. The paper presents the results of cascade codec architecture for FPGA using an internal LDPC code of DVB-S2 standard and outer Reed-Solomon code. The codec supports 6 coding rates and 2 frame lengths described in the annex of the standard. The proposed architecture of the decoder has a partially parallel structure, which allows to reach high decoding performance and effective utilization of the FPGA resources. In the decoder, an efficient algorithm of decoding was implemented with a reduced use of hardware resources. Moreover, it supports iterative “soft” decoding, which increases the likelihood of successful decoding. The use of concatenated coding allows to get rid of residual errors arising as a result of decoding of low-density code. It was also confirmed the presence of submatrices with double diagonals in the parity check matrices and a method for eliminating them was implemented. The authors analyzed the parameters that affect the static and dynamic power consumption. Based on it, algorithmic and architectural methods for reducing them are proposed. Paper contains description of the developed architectures, methods to increase productivity and reduce power consumption of the FPGA.

Keywords: FEC, LDPC, DVB-S2, FPGA, error floor, power consumption.

References

1. Gallager R. (1962). Low-density parity-check codes. IRE Transactions on information theory. Vol. 8. No. 1, pp. 21-28.
2. Vargauzin V.A. Tsikin I. A. (2013). Methods of increasing the energy and spectral efficiency of digital radio communications. BHV-Petersburg.
3. Zinchenko M.Y., Levadniy A.M., Grebenko Y.A. (2019). Concatenated error correction code implementation on FPGA. 2019 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO). IEEE, pp. 1-4.
4. Zinchenko M.Y., Levadniy A.M., Grebenko Y.A. (2018). Development of the LDPC coder-decoder of the DVB-S2 standard on FPGA. 2018 Systems of Signal Synchronization, Generating and Processing in Telecommunications (SYNCHROINFO). IEEE, pp. 1-3.
5. ETSI E. B. U. Digital video broadcasting (DVD); second generation framing structure, channel coding and modulation systems for broadcasting, interactive services, news gathering and other broadband satellite applications. Technical report, Tech. rep., ETSI, 2005.
6. H. Zhong, W. Xu, N. Xie, and T. Zhang, (2007). “Area-Efficient Min-Sum Decoder Design for High-Rate QC-LDPC Codes in Magnetic Recording,” IEEE Transactions on Magnetics. Vol. 43, No. 12, pp. 4117-4122, Dec. 2007.
7. C. Marchand, J-B Dore, L. Conde-Canencia and E. Boutillon, (2009). “Conflict Resolution by Matrix Reordering for DVB-T2 LDPC Decoders”, 2009 IEEE Global Telecommunications Conference (Honolulu, HI), pp. 1-6, Dec. 2009.
8. Tarasov I. (2009). Estimation of power consumption and choice of power supply system Xilinx FPGAs, Components and Technology, pp. 62-64, 02.2009.

Information about authors:

Maksim Y. Zinchenko, PhD student, assistant, Formation and processing of radio signals department National Research University “MPEI” Moscow, Russia
Alexey M. Levadniy, PhD student, Formation and processing of radio signals department National Research University “MPEI” Moscow, Russia
Yuri A. Grebenko, Professor, Formation and processing of radio signals department National Research University “MPEI” Moscow, Russia